Employment

Employment Summary (click to expand/collapse)

Title	Employer	Supervisor	Location	Dates
Lead Hardware Engineer	Schweitzer Engineering Laboratories, Inc.	Fred Jessup	Pullman, WA	Nov 2019 - Present
Hardware Engineer	Schweitzer Engineering Laboratories, Inc.	Fred Jessup	Pullman, WA	Nov 2015 - Nov 2019
Associate Hardware Engineer	Schweitzer Engineering Laboratories, Inc.	Fred Jessup	Pullman, WA	Jul 2014 - Nov 2015
Teaching Assistant	Brigham Young University - Idaho	Kevin Smith	Rexburg, ID	Jan 2014 - Jul 2014
Teaching Assistant	Brigham Young University - Idaho	Jason Rose	Rexburg, ID	Jan 2014 - Jul 2014
Hardware Engineer Intern	Schweitzer Engineering Laboratories, Inc.	Adrian Genz	Pullman, WA	Sep 2013 - Dec 2013
Software Engineer Intern	Schweitzer Engineering Laboratories, Inc.	Greg Rzepka	Pullman, WA	Apr 2013 - Sep 2013
Teaching Assistant	Brigham Young University - Idaho	Dave Brown	Rexburg, ID	Sep 2012 - Apr 2013
Program Developer	Brigham Young University - Idaho	Eric Karl	Rexburg, ID	Sep 2012 - Apr 2013
Math Tutor	Brigham Young University - Idaho	Daniel Baird	Rexburg, ID	Jan 2012 - Apr 2013
Teaching Assistant	Brigham Young University - Idaho	Ann Marie Harmon	Rexburg, ID	Sep 2011 - Dec 2011
Line Cook	Chili’s Grill & Bar	?	Greensboro, NC	Sep 2010 - Dec 2010
Line Cook/Expo	Applebee’s Grill & Bar	Glenn Stuebing	Denton, TX	Jan 2007 - Apr 2008
Line Cook	Fox’s Pizza Den	Mike King	Greer, SC	Aug 2005 - Jun 2006
Janitorial Asst.	D.R. Horton	Brian Belnap	Spartanburg, SC	Jun 2005 - Aug 2005

Lead Hardware Engineer

Schweitzer Engineering Laboratories, Inc., Pullman, WA

Nov 2019 - Present

Essential Duties and Responsibilities

1. Invents, analyzes and designs complex analog and digital circuits to meet specifications. Lead hardware design reviews to demonstrate product and circuit robustness.

2. Leads in the development of hardware and system level specifications of moderate complexity.

3. Writes and reviews test plans, executes or supervises testing, evaluates and reviews test results for use in peer reviews and for project notebooks.

4. Prepares and maintains accurate project or program plans. Provides detailed labor estimates.

5. Leads multiple projects or programs of moderate complexity. Participates in the executive project processes.

6. Leads engineers, associate engineers, and technicians in the product development processes. Mentors and coaches other engineers.

7. Follow and apply SEL Values, Principles of Operations, and World Class Manufacturing Principles.

8. Understand. Create. Simplify.

9. Other duties as assigned.

Projects

400G INT9

Hardware and Configurable Logic Development Team

The INT9 is an I/O peripheral board intended to extend functionality and add more capability to the 400G Generator Protection Relay. It houses 2 AOs, 6 AIs, 8 DIs, and 6 DOs, two of the DOs being “Aurora Proofed” with special logic implemented to withstand the Aurora Generator Test by disallowing successive output assertions in short bursts.

• Lead hardware designer for the INT9 analog/digital interface board.

• Extensive FIT rate analysis performed for selected FPGA. Since FPGA significantly contributed to board’s overall failure rate, it was heavily scrutinized by management.

• Circuit concepts reviewed and approved by Senior- and Principal-level engineers prior to design.

• Responsible for sampling/DSP scheme to maintain 16-bit resolution across a \(\pm\)40 mA, \(\pm\)2 mA, \(\pm\)1 V, or \(\pm\)10 V dynamic input range.

• Performed or supervised all circuit design aspects.

• Generated system- and board-level specifications.

• Heavily influenced RTL design and participating in review, verification, and demonstration activities.

• Used Synopsis’s Synpify Pro to synthesize radiation-tolerant logic using DWC and TMR (i.e., majority voting schemes) logic.

• Specified RTL fault-tolerant design approach.

• Designed a 3 Mbaud-capable UART in VHDL for real-time debug access to DSP chain.

• Worked with DAC supplier to improve and correct a plethora of datasheet errors and inconsistencies.

• Supervised/assisted intern in generating a Python interface to the debug UART.

• Troubleshot and corrected major EMI issues with isolated power supplies.

• Notable design experience:

  • Hardware Design:

    • High voltage (600+ V) isolation and digital signaling

    • Signal integrity

    • Circuit and interface timing analysis

    • Single-ended input to differential output analog input buffer

    • Isolated power supply design

    • High density I/O FPGA PCB layout

  • Digital & Configurable Logic Design:

    • Clock domain crossing analysis

    • Sinc decimation digital filtering

    • Signal integrity and termination resistor tweaking

    • HyperLynx simulation

    • Timing constraints/closure

  • Firmware/Software Design:

    • Python test interface to debug UART

      • Utilized unittest module for robust unit tests of python library.

      • Interfaced with UART (via pyserial)

      • Interfaced with oscilloscopes, voltage sources, function generators, DMMs, etc. via PyVISA.

      • Generated reports via XlsxWriter.

      • Distributed releases to internal PyPI mirror.

      • Analog inputs used to implement a real-time oscilloscope using matplotlib for dynamic waveform viewing.

      • Analog outputs used to drive an 8 \(\Omega\) speaker playing arbitrary audio files.

Fixed Point Python Package

At SEL, we modeled and tested configurable logic designs primarily using Python. DSP chains often use fixed-point arithmetic and generating a bit-accurate model for verification purposes has proven difficult.

While MATLAB’s Fixed Point Designer offers great tools for fixed point analysis and design, there was always a lack of available licenses, and it did not fit into our simulation flow very well.

Noticing the lack of legitimate fixed point tools available in Python, I decided to create one. Modeling it after MATLAB behavior and ensuring parallels between Python and VHDL constructs, the fixedpoint package was born and open-sourced.

The fixedpoint package offers several features that are widely used in DSP applications:

• Generate fixed point numbers from string literals, integers, or floating point numbers.

• Specify bit widths and signedness, or allow it to be deduced

• Various rounding methods

• Various overflow handling methods

• Configurable alerts for overflow, property mismatches, and implicit casting errors

• Arithmetic operations such as addition, subtraction, multiplication, exponentiation

• Bitwise operations AND, OR, XOR, and inversion.

• Type casting to int, float, bool, str

• Built-in string formatting (f-strings or str.format)

• Comparisons with other FixedPoint, int, or float objects

• The fixedpoint package is unit-tested against MATLAB stimulus (with the fixed point toolbox), making the fixedpoint package a viable, accurate, and cost-free alternative to MATLAB.

The fixedpoint package is released under the BSD license.

• Github Repository

• PyPI Download

• Documentation

Test Failure Analysis

In July 2019, SEL took some products to the TRIUMF Particle Accelerator Centre in Canada to determine their performance and failure modes when exposed to ionized radiation. Over several hours of testing a handful of products, there were hundreds of failures and tens of thousands of event records to sift through and make sense of. In 2019, that effort was performed manually by a small team over the course of four months. Management expressed their desire to do this experiment annually with different products, and the team knew that spending 1/3 of their year going through event files was not the best use of their time. I was tasked with automating this effort to cut down on the time and effort required to make sense of all the events.

I created a software utility in Python to parse the results and generate an summary Excel spreadsheet with events separated by product, sorted by timestamp, and event details conveniently shown in various columns. Additionally, event parsing, collating, and formatting was all configurable by way of a configuration file with simple parameters. Using the results from July 2019, the application takes about 2 minutes to wade through the data and generate a report, depending on the options specified in the configuration file.

Python Libraries Used:

• click to generate a command line interface.

• tqdm to provide progress bar feedback during parsing.

• sphinx to generate documentation

• xlsxwriter to generate an Excel spreadsheet report